Vintage Calc :: A delay-line memory calculator on an FPGA

The design revolves around the way the delay-line memory is organised. In concept, it can be seen as a stack of 4 registers, as shown in Table 1.

Each digit, in turn, consists of a stream of pulses, in 9 timing slots, with the pulse count corresponding to the digit value. The sign of each number is handled separately by a dedicated flip-flop and is displayed in the leftmost digit position.

The calculator logic is organised into modules, as follows: Timing unit, Memory unit, Display unit, Entry unit and Control unit. These modules are in turn interconnected in a top-level module, shown above. All logic is positive-edge triggered.

	Cascaded counters Provides addressing information for accessing the serial memory Drives all other modules Four-phase operation Deliberate ordering Prescales FPGA clock

	576-bit shift register Holds working memory Serial r/w access

	Drives the vector-drawn display Beam position Shift and stroke Blanking Generates: Decimal point Numerals 0-9 Blank, minus & overflow symbol Internally maintains: Pulse count for current digit

	Keyboard interface Scans key matrix Decodes and latches selected function or digit Hit / Ack mechanism Debouncing Drives buzzer

	Operation sequencing State machine Mini-operations Four phases per digit pulse period ALU is three 4-bit up/down counters Controls all calculator functions including keyboard entry phase

VintageCalc - A delay-line memory calculator on an FPGA